SDK • HSTX help to configure for 8-bit parallel transfer

Code:

             hstx_ctrl_hw->expand_tmds =        2  << HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB |        0  << HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB   |        2  << HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB |        29 << HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB   |        1  << HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB |        26 << HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB;        // 4 8-bit chunks. Control symbols (RAW) are an        // entire 32-bit word.        hstx_ctrl_hw->expand_shift =        4 << HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB |        8 << HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB |        1 << HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB |        0 << HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB;

Code:

    for (uint lane = 0; lane < 3; ++lane) {        // For each TMDS lane, assign it to the correct GPIO pair based on the        // desired pinout:        static const int lane_to_output_bit[3] = {0, 6, 4};        int bit = lane_to_output_bit[lane];        // Output even bits during first half of each HSTX cycle, and odd bits        // during second half. The shifter advances by two bits each cycle.        uint32_t lane_data_sel_bits =            (lane * 10    ) << HSTX_CTRL_BIT0_SEL_P_LSB |            (lane * 10 + 1) << HSTX_CTRL_BIT0_SEL_N_LSB;        // The two halves of each pair get identical data, but one pin is inverted.        hstx_ctrl_hw->bit[bit    ] = lane_data_sel_bits;        hstx_ctrl_hw->bit[bit + 1] = lane_data_sel_bits | HSTX_CTRL_BIT0_INV_BITS;    }

Code:

        for (uint lane = 0; lane < 8; ++lane) {            hstx_ctrl_hw->bit[lane]=lane;        }

Code:

        hstx_ctrl_hw->csr =            HSTX_CTRL_CSR_EXPAND_EN_BITS |            5u << HSTX_CTRL_CSR_CLKDIV_LSB |            5u << HSTX_CTRL_CSR_N_SHIFTS_LSB |            2u << HSTX_CTRL_CSR_SHIFT_LSB |            HSTX_CTRL_CSR_EN_BITS;         }

Code:

        hstx_ctrl_hw->csr =            1u << HSTX_CTRL_CSR_CLKDIV_LSB |            HSTX_CTRL_CSR_EN_BITS;         }