Hi,
I am trying to work out how to get multiple ISRs set up on 6 GPIO lines.
I have six external signals and I need a separate response for each one.
From what I have been able to ascertain, the STM core has 32 interrupts but only two are given to GPIO lines.
I did find someone suggesting doing some micro coding of the PIO statemachines but this is getting crazily complicated for such a trivial task. Is that really necessary?
At the very least , I could manage with one ISR if it knows which pin triggered the interrupt but I don't see how that would be available.
I get the feeling I'm misunderstanding what I've read or over looking something simple since this seems very complicated for an obvious IO requirement.
Can someone staighten me out please?
TIA.
I am trying to work out how to get multiple ISRs set up on 6 GPIO lines.
I have six external signals and I need a separate response for each one.
From what I have been able to ascertain, the STM core has 32 interrupts but only two are given to GPIO lines.
I did find someone suggesting doing some micro coding of the PIO statemachines but this is getting crazily complicated for such a trivial task. Is that really necessary?
At the very least , I could manage with one ISR if it knows which pin triggered the interrupt but I don't see how that would be available.
I get the feeling I'm misunderstanding what I've read or over looking something simple since this seems very complicated for an obvious IO requirement.
Can someone staighten me out please?
TIA.
Statistics: Posted by pie_face — Sun Aug 04, 2024 11:32 am — Replies 3 — Views 48