Hi,
I'm fiddling with a Pi Pico's MMIO and read about the atomic access registers (2.1.2). It's mentioned that "The SIO (Section 2.3.1), a single-cycle IO block attached directly to the cores' IO ports, does not support atomic accesses at the bus level, although some individual registers (e.g. GPIO) have set/clear/xor aliases."
I have two questions:
1. Why is that?
2. Out of curiosity I have tried setting IO_SIO_OE via the set mirror register and it appeared to work. Do those mirror still work, but with no atomic access?
I'm fiddling with a Pi Pico's MMIO and read about the atomic access registers (2.1.2). It's mentioned that "The SIO (Section 2.3.1), a single-cycle IO block attached directly to the cores' IO ports, does not support atomic accesses at the bus level, although some individual registers (e.g. GPIO) have set/clear/xor aliases."
I have two questions:
1. Why is that?
2. Out of curiosity I have tried setting IO_SIO_OE via the set mirror register and it appeared to work. Do those mirror still work, but with no atomic access?
Statistics: Posted by maldus — Mon Apr 01, 2024 6:23 pm — Replies 1 — Views 47
