I've tied my self in knots trying to understand adc_clk_div
From the datasheetSo assuming the ADC clock frequency is 48MHz then with the register set to 0 the conversion will take 2uS i.e. 96 clock cycles and if I do continuous conversions I will get 500K conversions/second
Now I want to get 200K conversions/second. What is the algorithm for determining the parameter to use in a call to adc_clk_div() ? Does the divider apply to each of the 96 samples or is it applied after all 96 have taken place at 48MHz.
To me the two bits of manual seem to imply the opposite and certainly don't explain my simple "user" requirement to achieve a specific sampling rate.
Clarification appreciated - thanks
From the datasheet
From the SDKClock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these fields are written.
Total period is 1 + INT + FRAC / 256
Code:
static void adc_set_clkdiv (float clkdiv) [inline], [static]Set the ADC Clock divisor.Period of samples will be (1 + div) cycles on average. Note it takes 96 cycles to perform a conversion, so any period lessthan that will be clamped to 96.Parametersclkdiv If non-zero, conversion will be started at intervals rather than back to back.Now I want to get 200K conversions/second. What is the algorithm for determining the parameter to use in a call to adc_clk_div() ? Does the divider apply to each of the 96 samples or is it applied after all 96 have taken place at 48MHz.
To me the two bits of manual seem to imply the opposite and certainly don't explain my simple "user" requirement to achieve a specific sampling rate.
Clarification appreciated - thanks
Statistics: Posted by matherp — Wed Feb 26, 2025 7:11 pm — Replies 1 — Views 34