Does the AI Hat+ require any connectivity to the GPIO header, or can everything be done over the PCIe port alone?
I'm thinking of a future compute module design that could utilize the AI Hat+ and won't have a GPIO header.
I'm thinking of a future compute module design that could utilize the AI Hat+ and won't have a GPIO header.
Statistics: Posted by JinShil — Fri Nov 22, 2024 2:38 am — Replies 4 — Views 61