I need to do some SPI transfers (transmit only) that I would like to be in the background.
I've tested DMA which works and I can set a DMA complete interrupt. However, once the DMA terminates I then have to wait for the SPI FIFO to empty and then purge the receive buffer and overflow flag (as in spi_write_blocking).
SPI doesn't have a TX FIFO empty interrupt which would be the obvious thing to use. Both CPUs are in use so I can't just have one of them waiting while the other gets on with processing.
Has anyone developed a decent background SPI mechanism they would share? Or, am I stuck with polling and purging once the DMA completes?
Any ideas appreciated.
Thanks
I've tested DMA which works and I can set a DMA complete interrupt. However, once the DMA terminates I then have to wait for the SPI FIFO to empty and then purge the receive buffer and overflow flag (as in spi_write_blocking).
SPI doesn't have a TX FIFO empty interrupt which would be the obvious thing to use. Both CPUs are in use so I can't just have one of them waiting while the other gets on with processing.
Has anyone developed a decent background SPI mechanism they would share? Or, am I stuck with polling and purging once the DMA completes?
Any ideas appreciated.
Thanks
Statistics: Posted by matherp — Tue Oct 08, 2024 4:07 pm — Replies 4 — Views 82